在运行DRC出现报错，怎样解决这个问题
Class Document Source Message Time Date No. [Silk To Solder Mask Clearance Constraint Violation] PCB1.PcbDoc Advanced PCB Silk To Solder Mask Clearance Constraint: (9.419mil < 10mil) Between Track (3815mil,3485mil)(3824mil,3485mil) on Top Overlay And Pad R1-2(3865mil,3485mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [9.419mil] 15:47:19 2020/3/17 2
第二种情况 Class Document Source Message Time Date No. [Minimum Solder Mask Sliver Constraint Violation] PCB1.PcbDoc Advanced PCB Minimum Solder Mask Sliver Constraint: (7.749mil < 10mil) Between Pad C1-1(3830mil,3279.528mil) on Top Layer And Pad C1-2(3830mil,3220.472mil) on Top Layer [Top Solder] Mask Sliver [7.749mil] 15:47:19 2020/3/17 10